Cycling to mitigate imprint in ferroelectric memories

ABSTRACT

The method includes storing a memory data state in the ferroelectric memory cell. An event will trigger the evaluation of signal margin on a memory cell. If the memory cell is identified to have a weak signal, the memory cell is exercised. Exercising includes either performing one or more data read/re-write events or performing one or more simulated data read and data write events of an alternating high data state and a low data state to the memory cell associated with the weak data bit. Both the lifetime retention testing and the memory data state exercising are performed in the background of normal memory operation.

FIELD OF INVENTION

The present invention relates generally to semiconductor devices andmore particularly to reduction of imprint for ferroelectricrandom-access memory (FRAM) arrays with low impact on memory systemavailability.

BACKGROUND OF THE INVENTION

In recent years the market of the semiconductor industry has grownconsiderably for supplying integrated chips to companies thatmanufacture portable electronic device. The integrated chips used tomake these portable electronic device, such as cell phones, PDAs, laptopcomputers and the like, are mostly made in emerging technology nodes.This is because emerging technology nodes offer higher density chipswith greater performance and lower power consumption. These qualitiesare important to portable electronic devices which are continuallystriving to offer greater functionality while relying on relativelysmall energy sources (e.g., batteries). The demand for these productshas driven the industry to devote many resources to developing low powerintegrated chips, often resulting in specific integration processes.

One aspect of power consumption in integrated circuits is the powerconsumption of memory cells. Memory can be broadly grouped into twocategories, volatile memory and non-volatile memory. Volatile memory(e.g., SRAM, DRAM) is memory which requires power to retain itsinformation. Non-volatile memory (e.g., EEPROM, flash) is memory whichdoes not require power to retain its information. In recent years, theuse of non-volatile memory has become common place in portableelectronics. Many portable electronic devices such as cell phones ordigital cameras will rely upon a stick or card which uses flash memoryas storage. Unfortunately, the performance and density of flash memoryand other wide spread commercially available non-volatile memory sourceslags behind that of volatile memory.

In recent years, semiconductor research has increased its emphasis onferroelectric memory as an alternative to commercially availablenon-volatile memories. Ferroelectric random-access memory (FRAM) is anon-volatile random access memory that offers advantages in terms ofpower consumption and write speed over existing non-volatile memorysources such as flash or EEPROM. There are still obstacles standing inthe way of FRAM becoming an important part of the memory market, but itspotential advantages point towards it as a possible contender for thefuture of non-volatile memory.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the invention. This summarypresents one or more concepts of the invention in a simplified form as aprelude to the more detailed description that is presented later and isnot an extensive overview of the invention. In this regard, the summaryis not intended to identify key or critical elements of the invention,nor does the summary delineate the scope of the invention.

One embodiment of the present invention relates to a method for reducingthe imprint of a ferroelectric memory cell. The method comprises storinga memory data state in the ferroelectric memory cell. An event willtrigger an evaluation of the signal margin of the memory cell. If thememory cell is identified to have a weak signal, the memory cell isexercised. Exercising comprises either performing one or more dataread/re-write events or performing one or more simulated data read anddata write events of an alternating high data state and a low data stateto the memory cell associated with the weak data bit. Both the signalmargin evaluation and the memory data state exercising are performed inthe background of normal memory operation.

An alternative embodiment of the present invention also relates to amethod for reducing the imprint of a ferroelectric memory cell. Themethod comprises storing a memory data state in the ferroelectric memorycell. An event will trigger the evaluation of signal margin of thememory cell. If the memory cell is identified to have a weak signal, amemory data state stored in the memory cell is rewritten to a separatememory location. The memory cell is then exercised by either performingone or more data read/re-write events or performing one or moresimulated data read and data write events of an alternating high datastate and a low data state to the memory cell associated with the weakdata bit. Once exercising is complete, the data state stored in theseparate memory location is re-written to the memory cell, thereforereturning the data state of the memory cell to its original data state.Additional embodiments of memory arrays and methods of inversion arealso disclosed.

The following description and annexed drawings set forth in detailcertain illustrative aspects and implementations of the invention. Theseare indicative of but a few of the various ways in which the principlesof the invention may be employed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows a basic 1T/1C ferroelectric memory cell;

FIG. 1B shows a basic 2T/2C ferroelectric memory cell;

FIG. 1C shows an exemplary hysteresis curve for a ferroelectricmaterial;

FIG. 2 shows an exemplary method for reading an FRAM memory cell;

FIG. 3 is a diagram illustrating an exemplary method of analyzingferroelectric data state degradation and lifetime;

FIG. 4 is a flow diagram of method of cycling data state of an FRAMmemory cell in accordance with an embodiment of the present invention;

FIG. 5 shows a graph of the percentage increase in signal strength of amemory cell as a function of the number of exercise cycles performed onthe cell after exposure to high temperature;

FIG. 6A shows a graph of the number of ferroelectric bits versus thereference signal applied for a capacitor with data states beingexercised at a low duty cycle;

FIG. 6B shows a graph of the number of ferroelectric bits versus thereference signal applied for a capacitor with data states beingexercised at a high duty cycle;

FIG. 7 is a flow diagram of an alternative method of exercising a datastate stored in a memory cell of FRAM memory array;

FIG. 8 is a flow diagram of an alternative method of exercising theentirety of data states stored in an FRAM array without signal marginevaluation; and

FIG. 9 is a block diagram of the FRAM memory cell with a controlcircuitry.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with reference to theattached drawing figures, wherein like reference numerals are used torefer to like elements throughout and wherein the illustrated structuresand devices are not necessarily drawn to scale.

FIG. 1A shows an exemplary single transistor, single capacitor (1T/1C)ferroelectric memory cell 100. This memory cell comprises aferroelectric capacitor 101 with a first terminal coupled to a plateline 105 and a second terminal coupled to a transistor 102. Thetransistor is further coupled to a bit line 103 and a word line 104 atits gate. When a voltage greater than the threshold voltage of thetransistor 102 is applied to the word line 104 the transistor 102 turnson, coupling the ferroelectric capacitor 101 to the bit line 103. Thebit line 103 is further coupled to a sense amplifier 106 which iscoupled to a reference voltage source 107. The reference voltage source107 provides a reference voltage. The sense amplifier 106 compares thereference voltage to the output of the bit line 103. If the bit voltageis higher than the reference voltage, the sense amplifier 106 will pullthe output voltage up. If the bit voltage is lower than the referencevoltage, the sense amplifier 106 will drive the output voltage down.

Variations in the architecture of memory cell 100 can also be used toform an FRAM memory cell. FIG. 1 B shows a double transistor, doublecapacitor (2T/2C) structure 108 which uses two transistors and twocapacitors to form FRAM memory cells, for example. The 2T/2C structurestores a bit and a complimentary bit in ferroelectric capacitors 101 and111, respectively. The bit is access by way of the word line 104 and thebit line 103. The complimentary bit is accessed by way of the word line104 and a complimentary bit line 109. Furthermore, depending on circuitarchitecture, the reference voltage source can comprise either a voltagereference generator or one or more reference capacitors integrated intothe memory array and coupled, through a bit line, to the sense amplifier105.

The methods and structures described in this disclosure are applicableto a 1T/1C ferroelectric memory cell, a 2T/2C ferroelectric memory cell,or other possible variations of FRAM architecture. Also, while thisdisclosure will refer to FRAM memory devices, it is understood that thememory devices may be other memory devices as well. For example, memorydevices may include memory cells having elements other thanferroelectric capacitive elements that may be affected by imprint ormemory devices that may be impacted by signal margin reduction due totime elapse or temperature exposure.

The ferroelectric capacitors used in FRAM memory cells comprise the samegeometric structure as traditional, dielectric filled, capacitors butuse ferroelectric material in place of the dielectric material.Ferroelectric materials undergo a polarization similar to dielectricmaterials upon subjection to an electric field. However, ferroelectricmaterials differ from dielectric materials in that, upon removal of theelectric field, they retain a degree of polarization. This is theproperty that allows ferroelectric capacitors to be used in non-volatilememory cells.

FIG. 1C shows a common hysteresis loop 120 for an FRAM memory cell. FRAMmemory cells are formed from capacitors which comprise a ferroelectricmaterial between their anode and cathode plates. The ferroelectricmaterial exhibits hysteresis as shown in FIG. 1C. Hysteresis propertiesare essential to the operation of FRAM memory cells. FIG. 1 illustratesa curve showing the total charge on the capacitor as a function of theapplied voltage. As the applied voltage changes, the charge stored onthe capacitor will follow the curve of FIG. 1C. For example, when avoltage, V1, is applied to the ferroelectric capacitor the dipoles ofthe ferroelectric material will polarize, storing a charge, Q1, on theferroelectric capacitor. When the applied voltage is removed, the chargeon the ferroelectric capacitor will follow the curve to the point Q2.Application of a negative voltage, V3, across the ferroelectriccapacitor will drive the charge stored along the curve to Q3. Uponremoval of the applied voltage a charge of Q4 will remain on theferroelectric capacitor. The charge remaining on the capacitor when itis at zero volts, Q2 or Q4, corresponds to data states of “0” or “1”.Therefore, FIG. 1C shows how data states are stored by a ferroelectriccapacitor in the absence of an applied voltage (i.e., in a non-volatilemanner).

FIG. 2 shows a prior art method 200 of reading from the ferroelectricmemory cell of FIG. 1A by applying voltages along the bit line, wordline, and plate line of the memory cell. At 202 the bit line 103associated with the memory cell that is to be read is pre-charged to 0V.The word line 104 is then activated at 204. The activation of the wordline 104 couples the bit line 103 to the ferroelectric capacitor 101. At206 the plate line 105 is pulsed enabling charge sharing between the bitline 103 and the ferroelectric capacitor 101. This charge sharingdischarges the ferroelectric capacitor 101 into the bit line 103 raisingthe voltage of the bit line 103. At 208 the sense amplifier 106 isturned on. The sense amplifier compares the voltage of the bit line 103to a reference voltage from the reference voltage generator 107 at 210.If the bit line voltage is above the reference voltage it will be pulledup. If the bit line voltage is below the reference voltage it will bedriven down.

Reading a high data state (i.e., “1”) from a ferroelectric memory cellis a destructive action (i.e., upon being read a “0” is written to allferroelectric capacitor cells). Therefore, a memory word must often berewritten to the ferroelectric capacitor 101 after it is read. At 212the bit line 103 is charged to a voltage that corresponds to the memorystate that was read from the memory cell coupled to the bit line 103.The plate line 105 is pulsed at 214, causing charge sharing between thebit line 103 and the ferroelectric capacitor 101. This charge sharingcharges the ferroelectric capacitor 101 to store the data stateassociated with the voltage of the bit line 103. After the pulse isover, at 216 the bit line 102 is driven to 0V. At 218 the word line 103is deactivated. Writing data to a ferroelectric memory cell is done in amanner similar to steps 212 to 218 of FIG. 2.

Imprint is the tendency of a ferroelectric capacitor which stays in thesame polarization state over a long period of time to preferentiallymaintain that state, weakening the ability to write and read thecomplement polarization state. Imprint has the effect of shifting thehysteresis loop of a ferroelectric material with respect to the appliedvoltage. This effect has important implications for ferroelectric memoryarrays. Over time, imprint will create a growing offset voltage whichdecreases signal margin between states and eventually makes distinctionof data states (e.g., “0” or “1”) impossible.

Imprint is one area which is commonly identified as a failure mechanismof FRAM memory. Different materials or memory cell architectures maydisplay more or less robust characteristics of reliability, but to someextent all materials will face some degradation due to imprint overtime. Elevated temperatures have also been shown to increase the rate atwhich imprint occurs.

One key to testing the impact that imprint has on FRAM memory cells isevaluating the signal margin of memory cells. One method of evaluationcomprises measuring the retention lifetime rates of data state withinthe memory cells. The retention lifetime rates provide a parameter bywhich the imprint degradation of ferroelectric memory cells can bemonitored. FIG. 3 shows an exemplary method for testing degradation of aferroelectric capacitor employing a first and a second ferroelectriccapacitor, referred to as CAP A and CAP B. The capacitors aredistinguished from each other as they will retain opposite data states.

In FIG. 3, testing is performed by writing a low data state (i.e., “0”)to CAP A and a high data state (i.e., “1”) to CAP B. Since capacitors Aand B are arbitrarily chosen, the data state assignment could bereversed. If the test is applied to a plurality of ferroelectric memorycells, data is often written into the FRAM array in a pattern of highand low data states. For example, a checkerboard pattern of “1's” and“0's” may be written into an FRAM array.

At 304 a bake is performed on the FRAM memory cells containing thewritten data states. The bake comprises exposing the memory cellcapacitors to an elevated temperature for a certain time period. Theelevated temperature of the bake will simulate a longer length of timeat normal operating temperatures and therefore accelerate imprint of theferroelectric memory cells. Therefore, in FIG. 3, CAP A will undergoimprint in a low data state and CAP B will undergo imprint in a highdata state. The time and temperature of the bake may vary depending onthe desired results. The longer the exposure time and the higher theexposure temperature the greater the imprint will be. An exemplary bakemay be performed at a temperature in the range of 105 to 250 degreesCelsius for 15 minutes to approximately 1000 hours.

The capacitors of the FRAM memory cells are read at 306. A methodsimilar to that of FIG. 2 may be utilized to read the memory cell. Ifthe capacitors are operating properly, CAP A should return a low datastate and CAP B should return a high data state. These states are knownas Same State (SS) data states since they are the same as the originaldata states written to the FRAM capacitors at 302.

At 308 the memory data states are restored. Restoring is the same asre-writing. Restoring is necessarily performed after a memory cellstoring a high data state is read since reading an FRAM cell is adestructive process. During retention lifetime testing, restoring alsoserves to simulate normal memory operation of memory cells.

The capacitors are then written to an opposite memory state in 310. Theopposite memory state is opposite the state that was written to acapacitor in 302. Therefore, at 310 CAP A is written to a high datastate (i.e., “1”) and CAP B is written to a low data state (i.e., “0”).

A delay for a selected amount of time is performed at 312. The delayused may be as low as 50 mS or as long as 10's of seconds. The delayallows the capacitors to reach a steady state.

At 314 the CAP A and CAP B are read again. If the capacitors areoperating properly CAP A will return a high data state and CAP B willreturn a low data state. These states are known as Opposite State (OS)data states since they are reversed from the original data states. Theferroelectric capacitors are restored again at 316. The process is thenrepeated.

The probability of CAP A and CAP B returning the proper data states(i.e., high and low, respectively, in our example) upon being read in314 is reduced due to the imprint caused by baking the capacitors at304. With each iteration of the process the imprint of the capacitorswill be increased by the baking step 304 and the probability of afailure will increase. In a practical situation, the process isperformed with a large number of memory cells which statistically causesfailures to occur at a greater rate. Retention lifetimes can bedetermined based upon data collected from repetition of this process.

For a 2T/2C memory architecture, an alternative method for identifyingweak memory cells comprises a method by which a diagnostic 1T/1Coperating mode is used to identify weak memory cells. Using a 1T/1Coperation allows the signal level for each bit of the 2T/2C architectureto be measured. In this method, a 1T/1C reference level is selected andintentionally set to a “guardbanded” level. The guardbanded level willbe set to a level that corresponds to a sufficiently strong data signal.The switching signal of a memory bit is read, using the 1T/1C operation.The read signal is compared to the guardbanded level. If the switchingsignal of the bit is weaker than the guardbanded level, the memory cellwould benefit from cycling.

FIG. 4 shows one embodiment of the present invention. This embodiment isa method 400 for improving reliability and performance of an FRAM memorycell. This method reduces the effect of imprint for an FRAM memory cellby exercising the data state stored in the cell. While method 400 isillustrated and described below as a series of acts or events, it willbe appreciated that the illustrated ordering of such acts or events arenot to be interpreted in a limiting sense. For example, some acts mayoccur in different orders and/or concurrently with other acts or eventsapart from those illustrated and/or described herein. In addition, notall illustrated acts may be required to implement one or more aspects orembodiments of the disclosure herein. Further, one or more of the actsdepicted herein may be carried out in one or more separate acts and/orphases.

At 402 a data state is stored in a memory cell. The storing of a datastate is done as part of the normal operation of the memory cell. It maybe initiated during manufacturing of the integrated chip to storeconfiguration data or it may be initiated by the user of an electronicdevice comprising the integrated chip. Therefore, 402 may be repeatedmany times prior to moving to 404. The control circuitry of theintegrated chip may store a data state by writing the data state to thememory cell using the method described in FIG. 2, for example. While 402references writing a single data state, this method may also be used fora plurality of ferroelectric memory data cells. In a practicalapplication this method of improving imprint for memory cells will beapplied to an entire FRAM memory array.

At 404 the system is queried as to whether a qualifying event hasoccurred. If a qualifying event occurs the method advances to 406. If aqualifying event has not occurred then step 404 will be repeated until aqualifying event does occur.

As referenced in this disclosure, the term qualifying event is meant tobroadly encompass a wide range of events that a manufacturer may want totrigger exercising the memory. Typically, qualifying events will bebased upon definite, predictable functions of the memory cell. Forexample, power-up or power down of the ferroelectric memory cell may beset as qualifying events which would trigger memory exercising. Inanother example, the elapse of a certain amount of time may be aqualifying event.

In alternative embodiments of the present invention, the memory cell maybe exercised when it is exposed to a high temperature environment (e.g.,105 C) or when its exposure to a high temperature environment is ended.In particular, configuration memory bits are often exposed to hightemperatures during manufacturing and assembly processes. Cycling ofmemory states during or after such processes would reduce the imprintdamage done to memory cells during exposure to the high temperature. Theinventors have contemplated a wide variety of other qualifying eventswhich may be useful to FRAM memory cells.

At 406 the signal margin of the memory cell is evaluated. Signal marginevaluation may comprise retention lifetime testing and can be performedaccording to the method of FIG. 3. In alternative embodiments, weaksignal strength may be evaluated by operating the memory cells atreduced voltages (below V_(dd)) or, for a 2T/2C architecture, by usingthe diagnostic 1T/1C operating mode. Signal evaluation determines if aweak signal data bit exists in the memory cell. A weak signal data bitis a bit which has a degraded signal margin due to imprint. A weaksignal data bit no longer possess a high level of polarization andtherefore fails to deliver a high signal margin. Depending on the levelof imprint such a memory cell may still be functional, but if leftunattended the level of signal margin will continue to decreaseeventually rendering the cell useless. In an alternative embodiment ofthe present invention 406 and/or 408 may be omitted and exercising thememory array may be performed on the entire memory array.

At 410 a memory cell comprising a weak signal data bits is exercised. Inone embodiment exercising the memory cell comprises performing one ormore simulated data read and data write events (e.g., read and writepulses) of an alternating high data state and a low data state to thememory cell associated with the weak data bit. In such an embodiment thecontent of the data state will be lost upon exercising the memory cell,therefore making this embodiment only applicable for exercising memorydata states which are storing non-critical information.

In an alternative embodiment exercising the data state comprisesperforming one or more data read/re-write events, whereby the same datastate is read and automatically re-written into the memory cellassociated with the weak data bit. For example, if the memory cell isstoring a “1”, the control circuitry would repeatedly read and re-writea “1” data state to the memory cell. Exercising the memory cell in thismanner can reduce imprint and reinforce the data state stored in thememory cell.

The manner in which exercising the memory cells is performed has a largeimpact on the results. In particular, both the number of exercise cyclesperformed and the rate of exercise cycling are important parameters inboth methods 400 and 700. By optimizing these parameters imprint can befurther reduced with minimal resource expenditure.

FIG. 5 shows a graph of the signal strength of an FRAM memory cell afterexposure to 150 C bake as a function of the number of exercise cyclesperformed on the cell. The results of this graph show that the imprintof a memory cell is logarithmically reduced as exercise cyclingincreases. An FRAM memory array that undergoes 100 cycles has an 8-9%increase in the signal strength from an unexercised FRAM memory array.However, increasing the number of cycles to 1000 will only increase thesignal strength of the FRAM memory array by 15-20%. Therefore, limitingthe number of exercise cycles used in 406 between 1 and 100 will providea significant gain in signal strength at a minimal expense of time andsystem resources. As used in this disclosure, the term exercise cyclesis intended to include the repetitive exercise acts of all embodimentsdisclosed in this specification. For example, re-writing the same datastate to a memory cell associated with a weak bit should be performedfor 1 to 100 pulses.

FIGS. 6A and 6B show the effects of exercise cycling speed onferroelectric capacitors exposed to a high temperature (e.g., 105 C or125 C). Both graphs, 6A and 6B, show two data sequences, one labeled preand one labeled post. The pre data sequence shows measurements taken ofa ferroelectric capacitor prior to a high temperature exposure of 125degrees Celsius for 500 hours. The post data sequence shows measurementstaken of the same ferroelectric capacitor after the high temperatureexposure. FIG. 6A shows the distribution of switched polarization signallevels in an FRAM memory array before and after exposure to a hightemperature, wherein the data states were cycled at a low duty cycle.FIG. 6B shows signal margin evaluation data taken from an FRAM memoryarray before and after exposure to a high temperature, wherein the datastates were cycled at a high duty cycle.

Comparison of the graphs shows that the FRAM capacitors undergoincreased signal reduction because of the effect of imprint when cyclingis performed at a low duty cycle. This effect can be attributed to theamount of time that a data state spends in a particular data state. If alow duty cycle is used the memory cell will remain in a particular datastate for a larger period of time than if a high duty cycle is used.Therefore, increasing the duty cycle of exercising in 410 will help tomaintain the signal strength and mitigate imprint related signalreduction.

FIGS. 6A and 6B also show that increased frequency of data cycling isespecially important to high density FRAM arrays, where the bit accessduty cycle is expected to be low (i.e., for a large memory array, it isexpected that individual bits will be accessed less frequently duringnormal use).

FIG. 7 shows an alternative embodiment of the present invention. Thisembodiment is a method 700 for improving reliability and performance ofFRAM memory cells storing critical data, where critical data refers todata users don't want to lose during exercising.

At 702 a data state is stored in a ferroelectric memory cell. As in 402,storage of the data state is part of the normal use of the memory andmay be repeated many times prior to 704.

At 704, the system waits for a qualifying event to occur. Once aqualifying occurs, the system evaluates the signal margin of theferroelectric memory cell at 706.

If a weak state is identified at 708, the data state stored in thememory cell is copied to another memory location at 710. For example, ifa “1” is stored in the memory cell, the control circuitry will write the“1” into a cache memory. Copying the data state to another memorylocation is done to ensure that the data stored in the memory locationis not lost while the memory cell is exercised. This embodiment isespecially important for information stored in memory cells which isnecessary to retain after exercising. For example, if code is stored inthe memory states the user may want to save the code prior to exercisingso that it is not lost.

Once the data state is safely stored in the memory location the memorycell is exercised at 712. As discussed earlier, exercising the memorycell is optimally performed at a high duty cycle for 1-100 cycles. At714, the data state stored in the memory location is rewritten to thememory cell. Therefore, the entire method 700 will reduce the imprint ofthe memory cell without losing the data stored in it.

To minimize the impact on memory performance the signal marginevaluation testing and exercise cycling of methods 400 and 700 areperformed in the background of normal memory operation. Running in sucha “background mode”, exercising the memory cells of the array istransparent to users of the array.

In an additional embodiment, method 700 will be applied to sub-sectionof the entire memory array. In this embodiment the memory arrayaddresses will be grouped into small blocks. Once a qualifying event hasoccurred, acts 706-714 will be performed on a single small block ofmemory address. When that memory address has been tested and exercisedthe control circuitry will go onto the next small block of memoryaddresses. Repeating this process, the control circuitry will test andexercise the entire memory array. By breaking the memory array up intosmaller sections, the amount of cache memory can be reduced to onlystore the memory data states of a sub-section of the memory arrayinstead of the entire array.

In an alternative embodiment of the present invention a bit accessmethod maintains an approximately uniform duty cycle by keeping track ofthe number of accesses to memory address locations. In this embodimentinfrequently used address locations are forced to exercise their data.This method causes minimal interruptions to normal memory operation asthe states are infrequently used. But, this method is especiallyimportant in reducing imprint because the rarely used cells targeted areespecially susceptible to imprint as they stay in a memory state for anextended period of time.

Another alternative embodiment of the present invention is shown in FIG.8. This method is similar to methods 400 and 700 except that in method800 the evaluation of the signal margin action (406, 706) of methods 400and 700 is omitted. If a time-independent qualifying event (e.g.,power-up, power down) is detected at 804, the entire plurality of memorycells comprising the memory array are exercised. For example, uponexposure to a high temperature, or any other qualifying event, allmemory cells in a memory array will undergo a single data read andre-write event (e.g., read pulse) or a single alternating data read anddata write event (e.g., read and write pulse) of an alternating highdata state and a low data state. This embodiment ensures that all bitsof a memory array are exercised upon experiencing a qualifying event.

In an additional alternative embodiment of the present invention theentire plurality of memory cells comprising the memory array willundergo a single data read and re-write event (e.g., read pulse) to asingle data state upon the occurrence of a qualifying event, wherein thequalifying event is a predetermined time event (e.g., the FRAM array isexercised every 7 days, 30 days, etc.). The predetermined time event maybe set by a user.

FIG. 9 shows a block diagram of a memory organization 900. The memoryarray 902 is connected to row 904 and column 906 decoders, which routeinformation to and from addresses within the memory array. The decoders,904 and 906, are connected to an input/output (I/O) interfaces 908, 909.Furthermore, a control circuitry 910 is included. The control circuitryis important in implementation of the above embodiments. It checks tomake sure that a qualifying event has occurred, performs signal marginevaluation and accordingly exercises memory cells with weak data statesignal strength. In this diagram the control circuitry 910 indirectlyreceives an address and payload information from the memory array 902.From this information the control circuitry 910 may monitor at what timeaddresses and payloads have been inverted and decide if either aninversion process needs to begin. In another embodiment an optionaltemperature monitor 912 is added which provides a signal to the controlcircuitry 910 if the temperature exceeds a predetermined temperaturerange.

Although the invention has been illustrated and described with respectto one or more implementations, alterations and/or modifications may bemade to the illustrated examples without departing from the spirit andscope of the appended claims. In particular regard to the variousfunctions performed by the above described components or structures(assemblies, devices, circuits, systems, etc.), the terms (including areference to a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component or structurewhich performs the specified function of the described component (e.g.,that is functionally equivalent), even though not structurallyequivalent to the disclosed structure which performs the function in theherein illustrated exemplary implementations of the invention. Inaddition, while a particular feature of the invention may have beendisclosed with respect to only one of several implementations, suchfeature may be combined with one or more other features of the otherimplementations as may be desired and advantageous for any given orparticular application. Furthermore, to the extent that the terms“including”, “includes”, “having”, “has”, “with”, or variants thereofare used in either the detailed description and the claims, such termsare intended to be inclusive in a manner similar to the term“comprising”.

1. A method, comprising: detecting an occurrence of a qualifying event;evaluating a signal margin of a ferroelectric memory cell located withina ferroelectric random access memory (FRAM) array upon the occurrence ofthe qualifying event and identifying whether or not the ferroelectricmemory cell comprises a weak signal bit; copying a ferroelectric memorydata state associated with the weak signal bit from the ferroelectricmemory cell to an alternative memory data state in an alternative memorylocation prior to exercising the ferroelectric memory cell associatedwith the weak signal bit; exercising the ferroelectric memory cellassociated with the weak signal bit; and writing the alternative memorydata state to the ferroelectric memory data state in the ferroelectricmemory cell associated with the weak signal bit after the exercising theferroelectric memory cell associated with the weak signal bit iscompleted; wherein exercising the ferroelectric memory cell is performedby applying one or more data read/re-write pulses or one two or morealternating high state and low state data read and data write pulses tothe ferroelectric memory cell associated with the weak signal bit. 2.The method of claim 1, further comprising: storing a ferroelectricmemory data state in the ferroelectric memory cell prior to detectingthe occurrence of the qualifying event.
 3. The method of claim 1 whereina control circuitry utilizes a result of the evaluation to determinewhether or not exercising of the ferroelectric memory cell is needed. 4.The method of claim 1, wherein exercising the ferroelectric memory cellis performed between 1-100 exercise cycles.
 5. The method of claim 4,wherein evaluating the signal margin of the ferroelectric memory datastate is performed in the background of normal FRAM array operation andwherein exercising the ferroelectric memory cell comprising the weaksignal bit is performed in the background of normal FRAM arrayoperation.
 6. The method of claim 4, further comprising: storing anumber of accesses to a memory address location; and forcing exercisingto be performed on the ferroelectric memory cell associated with thememory address location with a low number of accesses.
 7. The method ofclaim 4, further comprising: dividing the FRAM array into a plurality ofmemory sub-sections prior to evaluating the signal margin and exercisingthe ferroelectric memory cell, wherein evaluating the signal margin andexercising the ferroelectric memory cell are only performed on one ofthe plurality of memory sub-sections at a time.
 8. The method of claim4, wherein exercising the ferroelectric memory cell comprises performingone or more simulated data read and data write pulses of a high datastate and a low data state.
 9. The method of claim 4, wherein exercisingthe ferroelectric memory cell comprises reading/re-writing a memory datastate associated with the ferroelectric memory cell one or more times.10. The method of claim 4, wherein the qualifying event comprises: apower up of the FRAM array or a power-down of the FRAM array.
 11. Themethod of claim 4, wherein the qualifying event comprises detectingexposure of the FRAM array to a high temperature, and wherein exercisingthe ferroelectric memory cell associated with the weak signal bit isperformed while the FRAM array is at the high temperature.
 12. Themethod of claim 4, wherein the qualifying event comprises the FRAM arrayreturning from a high temperature exposure to a non-high temperatureexposure, and wherein exercising the ferroelectric memory cellassociated with the weak signal bit is performed after the FRAM arrayhas returned to the non-high temperature.
 13. The method of claim 4,wherein the FRAM array comprises a 2T/2C memory array.
 14. The method ofclaim 13, wherein evaluating the signal margin of the 2T/2C memory arrayis performed using a diagnostic 1T/1C operating mode, comprising:selecting a 1T/1C reference level, wherein the 1T/1C reference levelcorresponds to a memory data state signal of a properly functioningferroelectric memory cell; reading a switching signal of theferroelectric memory cell using a 1T/1C operation; and comparing theswitching signal of the ferroelectric memory cell to the 1T/1C referencelevel, wherein the ferroelectric memory cell is exercised if theswitching signal is smaller than the 1T/1C reference level.
 15. Amethod, comprising: detecting an occurrence of a time independentqualifying event of a ferroelectric random access memory arraycontaining a plurality of ferroelectric memory cells; copyingferroelectric memory data states from the plurality of ferroelectricmemory cells to alternative memory data states in a plurality ofalternative memory locations prior to exercising the plurality offerroelectric memory cells; exercising the plurality of ferroelectricmemory cells; and writing the alternative memory data states to theferroelectric memory data states in the plurality of ferroelectricmemory cells after the exercising is completed; wherein exercising theplurality of ferroelectric memory cells is performed by applying one ormore data read/re-write pulses or one or more alternating data read anddata write pulses to the entire plurality of ferroelectric memory cellscomprising the FRAM array.
 16. A method, comprising: detecting anoccurrence of a qualifying event of a ferroelectric random access memoryarray containing a plurality of ferroelectric memory cells, wherein thequalifying event comprises a predetermined time; copying ferroelectricmemory data states from the plurality of ferroelectric memory cells toalternative memory data states in a plurality of alternative memorylocations prior to exercising the plurality of ferroelectric memorycells; exercising the plurality of ferroelectric memory cells; andwriting the alternative memory data states to the ferroelectric memorydata states in the plurality of ferroelectric memory cells after theexercising is completed; wherein exercising the plurality offerroelectric memory cells comprises reading/re-writing a memory datastate to the entire plurality of ferroelectric memory cells comprisingthe FRAM array one or more times.